40MX and 42MX FPGA Families
1-82 Revision 11
TTL Output Module Timing
5
t
ENLZ
Enable Pad LOW to Z 6.9 7.6 8.7 10.2 14.3 ns
t
GLH
G-to-Pad HIGH 4.9 5.5 6.2 7.3 10.2 ns
t
GHL
G-to-Pad LOW 4.9 5.5 6.2 7.3 10.2 ns
t
LSU
I/O Latch Output Set-Up 0.7 0.7 0.8 1.0 1.4 ns
t
LH
I/O Latch Output Hold 0.0 0.0 0.0 0.0 0.0 ns
t
LCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
7.9 8.8 10.0 11.8 16.5 ns
t
ACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
10.9 12.1 13.7 16.1 22.5 ns
d
TLH
Capacitive Loading, LOW to HIGH 0.10 0.11 0.12 0.14 0.20 ns/pF
d
THL
Capacitive Loading, HIGH to LOW 0.10 0.11 0.12 0.14 0.20 ns/pF
CMOS Output Module Timing
5
t
DLH
Data-to-Pad HIGH 4.9 5.5 6.2 7.3 10.3 ns
t
DHL
Data-to-Pad LOW 3.4 3.8 4.3 5.1 7.1 ns
t
ENZH
Enable Pad Z to HIGH 3.7 4.1 4.7 5.5 7.7 ns
t
ENZL
Enable Pad Z to LOW 4.1 4.6 5.2 6.1 8.5 ns
t
ENHZ
Enable Pad HIGH to Z 7.4 8.2 9.3 10.9 15.3 ns
t
ENLZ
Enable Pad LOW to Z 6.9 7.6 8.7 10.2 14.3 ns
t
GLH
G-to-Pad HIGH 7.0 7.8 8.9 10.4 14.6 ns
t
GHL
G-to-Pad LOW 7.0 7.8 8.9 10.4 14.6 ns
t
LSU
I/O Latch Set-Up 0.7 0.7 0.8 1.0 1.4 ns
t
LH
I/O Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
t
LCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
7.9 8.8 10.0 11.8 16.5 ns
Table 1-39 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, T
J
= 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Parameter / Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for d elay f rom an e xtern al PAD s ignal t o the G inputs . Delay f rom an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.