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A40MX02-BGG208

A40MX02-BGG208首页预览图
型号: A40MX02-BGG208
PDF文件:
  • A40MX02-BGG208 PDF文件
  • A40MX02-BGG208 PDF在线浏览
功能描述: 40MX and 42MX FPGA Families
PDF文件大小: 7439.21 Kbytes
PDF页数: 共142页
制造商: MICROSEMI[Microsemi Corporation]
制造商LOGO: MICROSEMI[Microsemi Corporation] LOGO
制造商网址: http://www.microsemi.com
捡单宝A40MX02-BGG208
PDF页面索引
120%
40MX and 42MX FPGA Families
1-76 Revision 11
Global Clock Network
t
CKH
Input LOW to HIGH FO = 32
FO = 635
2.7
3.0
3.0
3.3
3.4
3.8
4.0
4.4
5.6
6.2
ns
ns
t
CKL
Input HIGH to LOW FO = 32
FO = 635
3.8
4.9
4.2
5.4
4.8
6.1
5.6
7.2
7.8
10.1
ns
ns
t
PWH
Minimum Pulse
Width HIGH
FO = 32
FO = 635
1.8
2.0
2.0
2.2
2.2
2.5
2.6
2.9
3.6
4.1
ns
ns
t
PWL
Minimum Pulse
Width LOW
FO = 32
FO = 635
1.8
2.0
2.0
2.2
2.2
2.5
2.6
2.9
3.6
4.1
ns
ns
t
CKSW
Maximum Skew FO = 32
FO = 635
0.8
0.8
0.8
0.8
0.9
0.9
1.0
1.0
1.4
1.4
ns
ns
t
SUEXT
Input Latch External
Set-Up
FO = 32
FO = 635
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
t
HEXT
Input Latch External
Hold
FO = 32
FO = 635
2.8
3.3
3.2
3.7
3.6
4.2
4.2
4.9
5.9
6.9
ns
ns
t
P
Minimum Period
(1/f
MAX
)
FO = 32
FO = 635
5.5
6.0
6.1
6.6
6.6
7.2
7.6
8.3
12.7
13.8
ns
ns
f
MAX
Maximum Datapath
Frequency
FO = 32
FO = 635
180
166
164
151
151
139
131
121
79
73
MHz
MHz
TTL Output Module Timing
5
t
DLH
Data-to-Pad HIGH 2.6 2.8 3.2 3.8 5.3 ns
t
DHL
Data -to -Pa d LOW 3.0 3.3 3.7 4.4 6.2 ns
t
ENZH
Enable Pad Z to HIGH 2.7 3.0 3.3 3.9 5.5 ns
t
ENZL
Enable Pad Z to LOW 3.0 3.3 3.7 4.3 6.1 ns
t
ENHZ
Enable Pad HIGH to Z 5.3 5.8 6.6 7.8 10.9 ns
Table 1-38 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T
J
= 70°C)
–3 Sp eed –2 Speed –1 Speed St d Speed –F Speed
Parameter / Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold ti mi ng parame ters must acc ount fo r de lay fr om an ex ternal PAD sig nal to the G inpu ts . Dela y from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
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