40MX and 42MX FPGA Families
1-4 Revision 11
provides capability to quickly design memory functions with the SRAM blocks. Unused SRA M blocks can
be used to implement registers for other user logic within the design.
Routing Structure
The MX architecture uses vertical and horizontal routing tracks to interconnect the various logic and I/O
modules. These routing tracks are metal interconnects that may be continuous or split into segments.
Varying segment lengths allow the interconnect of over 90% of design tracks to occur with only two
antifuse connections. Segments can be joined together at the ends using antifuses to increase their
lengths up to the full length of the track. All interconnects can be accomplishe d with a maximum of four
antifuses.
Horizontal Routing
Horizontal routing tracks sp an the whole row length or are divided into multiple segments and are located
in between the rows of modules. Any segment that spans more than one-third of the row length is
considered a long horizontal segment. A typical channel is shown in Figure 1-6. Within horizontal routing,
dedicated routing tracks are used for global clock networks and for power and ground tie-off tracks. Non-
dedicated tracks are used for signal nets.
Vertical Routing
Another set of routing tracks run vertically th rough the module. There are three types of vertic al tracks:
input, output, and long. Long tracks span the column length of the module, and can be divided into
multiple segments. Each segment in an input track is d edicated to the input of a particular module; each
segment in an output track is dedicated to the output of a particular module. Long segments are
Figure 1- 4 • A42MX24 and A42MX36 D-Module Implementa tion
Figure 1- 5 • A42MX36 Dual-Port SRAM Block
7 Inputs
Hard-Wire to I/O
Feedback to Array
Programmable
Inverter
SRAM Module
32 x 8 or 64 x 4
(256 Bits)
Read
Port
Logic
Write
Port
Logic
RD[7: 0]
Routing Tracks
Latches
Read
Logic
[5:0]
RDAD[5:0]
REN
RCLK
Latches
WD[7: 0]
Latches
WRAD[5:0]
Write
Logic
MOD E
BLKEN
WEN
WCLK
[5:0]
[7:0]
