40MX and 42MX FPGA Families
1-74 Revision 11
Table 1-38 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T
J
= 70°C)
–3 Sp eed –2 Speed –1 Speed St d Speed –F Speed
Parameter / Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Combinatorial Functions
1
t
PD
Internal Array Module Delay 1.3 1.5 1.7 2.0 2.7 ns
t
PDD
Internal Decode Module Delay 1.6 1.8 2.0 2.4 3.3 ns
Logic Module Predicted Routing Delays
2
t
RD1
FO = 1 Routing Delay 0.9 1.0 1.2 1.4 2.0 ns
t
RD2
FO = 2 Routing Delay 1.3 1.4 1.6 1.9 2.7 ns
t
RD3
FO =3 Routing Delay 1.6 1.8 2.0 2.4 3.4 ns
t
RD4
FO = 4 Routing Delay 2.0 2.2 2.5 2.9 4.1 ns
t
RD5
FO = 8 Routing Delay 3.3 3.7 4.2 4.9 6.9 ns
t
RDD
Decode-to-Output Routing Delay 0.3 0.4 0.4 0.5 0.7 ns
Logic Module Sequential Timing
3, 4
t
CO
Flip-Flop Clock-to-Output 1.3 1.4 1.6 1.9 2.7 ns
t
GO
Latch Gate-to-Output 1.3 1.4 1.6 1.9 2.7 ns
t
SUD
Flip-Flop (Latch) Set-Up T i me 0.3 0.3 0.4 0.5 0.7 ns
t
HD
Flip-Flop (Latch) Hold Time 0.0 0.0 0.0 0.0 0.0 ns
t
RO
Flip-Flop (Latch) Reset-to-Output 1.6 1.7 2.0 2.3 3.2 ns
t
SUENA
Flip-Flop (Latch) Enable Set-Up 0.7 0.8 0.9 1.0 1.4 ns
t
HENA
Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 0.0 ns
t
WCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
3.3 3.7 4.2 4.9 6.9 ns
t
WASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
4.4 4.8 5.5 6.4 9.0 ns
Synchronous SRAM Ope ra tions
t
RC
Read Cycle Time 6.8 7.5 8.5 10.0 14.0 ns
t
WC
Write Cycle Time 6.8 7.5 8.5 10.0 14.0 ns
t
RCKHL
Clock HIGH/LOW T ime 3.4 3.8 4.3 5.0 7.0 ns
t
RCO
Data Valid After Clock HI GH/LOW 3.4 3.8 4.3 5.0 7.0 ns
t
ADSU
Address/Data Set-Up T ime 1.6 1.8 2.0 2.4 3.4 ns
Synchronous SRAM Ope ra tions (continued)
t
ADH
Address/Data Hold Time 0.0 0.0 0.0 0.0 0.0 ns
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold ti mi ng parame ters must acc ount fo r de lay fr om an ex ternal PAD sig nal to the G inpu ts . Dela y from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.