• 当前位置:
  • 首页
  • >
  • PDF资料
  • >
  • A40MX02-BGG208 PDF文件及第77页内容在线浏览

A40MX02-BGG208

A40MX02-BGG208首页预览图
型号: A40MX02-BGG208
PDF文件:
  • A40MX02-BGG208 PDF文件
  • A40MX02-BGG208 PDF在线浏览
功能描述: 40MX and 42MX FPGA Families
PDF文件大小: 7439.21 Kbytes
PDF页数: 共142页
制造商: MICROSEMI[Microsemi Corporation]
制造商LOGO: MICROSEMI[Microsemi Corporation] LOGO
制造商网址: http://www.microsemi.com
捡单宝A40MX02-BGG208
PDF页面索引
120%
40MX and 42MX FPGA Families
Revision 11 1-73
TTL Output Module Timing
5
(continued)
t
LH
I/O Latch Output Hold 0.0 0.0 0.0 0.0 0.0 ns
t
LCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
7.7 8.5 9.6 11.3 15.9 ns
t
ACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
14.8 16.5 18.7 22.0 30.8 ns
d
TLH
Capacitive Loading, LOW to HIGH 0.05 0.05 0.06 0.07 0.10 ns/pF
d
THL
Capacitive Loading, HIGH to LOW 0.04 0.04 0.05 0.06 0.08 ns/pF
CMOS Output Module Timing
5
t
DLH
Data-to-Pad HIGH 4.8 5.3 5.5 6.4 9.0 ns
t
DHL
Data-to-Pad LOW 3.5 3.9 4.1 4.9 6.8 ns
t
ENZH
Enable Pad Z to HIGH 3.6 4.0 4.5 5.3 7.4 ns
t
ENZL
Enable Pad Z to LOW 3.4 4.0 5.0 5.8 8.2 ns
t
ENHZ
Enable Pad HIGH to Z 7.2 8.0 9.0 10.7 14.9 ns
t
ENLZ
Enable Pad LOW to Z 6.7 7.5 8.5 9.9 13.9 ns
t
GLH
G-to-Pad HIGH 6.8 7.6 8.6 10.1 14.2 ns
t
GHL
G-to-Pad LOW 6.8 7.6 8.6 10.1 14.2 ns
t
LSU
I/O Latch Set-Up 0.7 0.7 0.8 1.0 1.4 ns
t
LH
I/O Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
t
LCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
7.7 8.5 9.6 11.3 15.9 ns
t
ACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
14.8 16.5 18.7 22.0 30.8 ns
d
TLH
Capacitive Loading, LOW to HIGH 0.05 0.05 0.06 0.07 0.10 ns/pF
d
THL
Capacitive Loading, HIGH to LOW 0.04 0.04 0.05 0.06 0.08 ns/pF
t
HEXT
Input Latch External
Hold
FO = 32
FO = 486
3.9
4.6
4.3
5.2
4.9
5.8
5.7
6.9
8.1
9.6
ns
ns
t
P
Minimum Period
(1/f
MAX
)
FO = 32
FO = 486
7.8
8.6
8.7
9.5
9.5
10.4
10.8
11.9
18.2
19.9
ns
ns
Table 1-37 • A42MX24 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, T
J
= 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsParameter / Description M in. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for d elay f rom an e xtern al PAD s ignal t o the G inputs . Delay f rom an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
购买、咨询产品请填写询价信息:(3分钟左右您将得到回复)
询价型号*数量*批号封装品牌其它要求
删除
删除
删除
删除
删除
增加行数
  •  公司名:
  • *联系人:
  • *邮箱:
  • *电话:
  •  QQ:
  •  微信:

  • 关注官方微信

  • 联系我们
  • 电话:13714778017
  • 周一至周六:9:00-:18:00
  • 在线客服:

天天IC网由深圳市四方好讯科技有限公司独家运营

天天IC网 ( www.ttic.cc ) 版权所有©2014-2023 粤ICP备15059004号

因腾讯功能限制,可能无法唤起QQ临时会话,(点此复制QQ,添加好友),建议您使用TT在线询价。

继续唤起QQ 打开TT询价