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A40MX02-BGG208

A40MX02-BGG208首页预览图
型号: A40MX02-BGG208
PDF文件:
  • A40MX02-BGG208 PDF文件
  • A40MX02-BGG208 PDF在线浏览
功能描述: 40MX and 42MX FPGA Families
PDF文件大小: 7439.21 Kbytes
PDF页数: 共142页
制造商: MICROSEMI[Microsemi Corporation]
制造商LOGO: MICROSEMI[Microsemi Corporation] LOGO
制造商网址: http://www.microsemi.com
捡单宝A40MX02-BGG208
PDF页面索引
120%
40MX and 42MX FPGA Families
Revision 11 1-71
Table 1-37 • A42MX24 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, T
J
= 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsParameter / Description M in. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Logic Module Combinatorial Functions
1
t
PD
Internal Array Module Delay 2.0 1.8 2.1 2.5 3.4 ns
t
PDD
Internal Decode Module Delay 1.1 2.2 2.5 3.0 4.2 ns
Logic Module Predicted Routing Delays
2
t
RD1
FO = 1 Routing Delay 1.7 1.3 1.4 1 .7 2.3 ns
t
RD2
FO = 2 Routing Delay 2.0 1.6 1.8 2 .1 3.0 ns
t
RD3
FO = 3 Routing Delay 1.1 2.0 2.2 2 .6 3.7 ns
t
RD4
FO = 4 Routing Delay 1.5 2.3 2.6 3 .1 4.3 ns
t
RD5
FO = 8 Routing Delay 1.8 3.7 4.2 5 .0 7.0 ns
Logic Module Sequential Timing
3, 4
t
CO
Flip-Flop Clock-to-Output 2.1 2.0 2.3 2.7 3.7 ns
t
GO
Latch Gate-to-Output 3.4 1.9 2.1 2.5 3.4 ns
t
SUD
Flip-Flop (Latch) Set-Up Time 0.4 0.5 0.6 0.7 0.9 ns
t
HD
Flip-Flop (Latch) Hold Time 0.0 0.0 0.0 0.0 0.0 ns
t
RO
Flip-Flop (Latch) Reset-to-Output 2.0 2.2 2.5 2.9 4.1 ns
t
SUENA
Flip-Flop (Latch) Enable Set-Up 0.6 0.6 0.7 0.8 1.2 ns
t
HENA
Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 0.0 ns
t
WCLKA
Flip-Flop (Latch)
Clock Active Pulse Width
4.6 5.2 5.8 6.9 9.6 ns
t
WASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
6.1 6.8 7.7 9.0 12.6
ns
Input Module Propagation Delays
t
INPY
Input Data Pad-to-Y 1.4 1.6 1.8 2.2 3.0 ns
t
INGO
Input Latch Gate-to-Output 1.8 1.9 2.2 2.6 3.6 ns
t
INH
Input Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
t
INSU
Input Latch Set-Up 0.7 0.7 0.8 1.0 1.4 ns
t
ILA
Latch Active Pulse Width 6.5 7.3 8.2 9.7 13.5 ns
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for d elay f rom an e xtern al PAD s ignal t o the G inputs . Delay f rom an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
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