40MX and 42MX FPGA Families
Revision 11 1-69
TTL Output Module Timing
5
t
DLH
Data-to-Pad HIGH 2.4 2.7 3.1 3.6 5.1 ns
t
DHL
Data-to-Pad LOW 2.8 3.2 3.6 4.2 5.9 ns
t
ENZH
Enable Pad Z to HIGH 2.5 2.8 3.2 3.8 5.3 ns
t
ENZL
Enable Pad Z to LOW 2.8 3.1 3.5 4.2 5.9 ns
t
ENHZ
Enable Pad HIGH to Z 5.2 5.7 6.5 7.6 10.7 ns
t
ENLZ
Enable Pad LOW to Z 4.8 5.3 6.0 7.1 9.9 ns
t
GLH
G-to-Pad HIGH 2.9 3.2 3.6 4.3 6.0 ns
t
GHL
G-to-Pad LOW 2.9 3.2 3.6 4.3 6.0 ns
t
LSU
I/O Latch Output Set-Up 0.5 0.5 0.6 0.7 1.0 ns
t
LH
I/O Latch Output Hold 0.0 0.0 0.0 0.0 0.0 ns
t
LCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
5.6 6.1 6.9 8.1 11.4 ns
t
ACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
10.6 11.8 13.4 15.7 22.0 ns
d
TLH
Capacitive Loading, LOW to HIGH 0.04 0.04 0.04 0.05 0.07 ns/pF
d
THL
Capacitive Loading, HIGH to LOW 0.03 0.03 0.03 0.04 0.06 ns/pF
Table 1-36 • A42MX24 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T
J
= 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Parameter / Description Min. Max. Min. Max. Min. Max. Min. Ma x. Min. Max. Units
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold ti mi ng parame ters must acc ount fo r de lay fr om an extern al PAD sig nal to the G inpu ts . Dela y from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.