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A40MX02-BGG208

A40MX02-BGG208首页预览图
型号: A40MX02-BGG208
PDF文件:
  • A40MX02-BGG208 PDF文件
  • A40MX02-BGG208 PDF在线浏览
功能描述: 40MX and 42MX FPGA Families
PDF文件大小: 7439.21 Kbytes
PDF页数: 共142页
制造商: MICROSEMI[Microsemi Corporation]
制造商LOGO: MICROSEMI[Microsemi Corporation] LOGO
制造商网址: http://www.microsemi.com
捡单宝A40MX02-BGG208
PDF页面索引
120%
40MX and 42MX FPGA Families
1-68 Revision 11
Input Module Predicted Routing Delays
2
t
IRD1
FO = 1 Routing Delay 1.8 2.0 2.3 2.7 3.8 ns
t
IRD2
FO = 2 Routing Delay 2.1 2.3 2.6 3.1 4.3 ns
t
IRD3
FO = 3 Routing Delay 2.3 2.5 2.9 3.4 4.8 ns
t
IRD4
FO = 4 Routing Delay 2.5 2.8 3.2 3.7 5.2 ns
t
IRD8
FO = 8 Routing Delay 3.4 3.8 4.3 5.1 7.1 ns
Global Clock Network
t
CKH
Input LOW to HIGH FO = 32
FO = 486
2.6
2.9
2.9
3.2
3.3
3.6
3.9
4.3
5.4
5.9
ns
ns
t
CKL
Input HIGH to LOW FO = 32
FO = 486
3.7
4.3
4.1
4.7
4.6
5.4
5.4
6.3
7.6
8.8
ns
ns
t
PWH
Minimum Pulse
Width HIGH
FO = 32
FO = 486
2.2
2.4
2.4
2.6
2.7
3.0
3.2
3.5
4.5
4.9
ns
ns
t
PWL
Minimum Pulse
Width LOW
FO = 32
FO = 486
2.2
2.4
2.4
2.6
2.7
3.0
3.2
3.5
4.5
4.9
ns
ns
t
CKSW
Maximum Skew FO = 32
FO = 486
0.5
0.5
0.6
0.6
0.7
0.7
0.8
0.8
1.1
1.1
ns
ns
t
SUEXT
Input Latch External
Set-Up
FO = 32
FO = 486
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
t
HEXT
Input Latch External
Hold
FO = 32
FO = 486
2.8
3.3
3.1
3.7
3.5
4.2
4.1
4.9
5.7
6.9
ns
ns
t
P
Minimum Period
(1/f
MAX
)
FO = 32
FO = 486
4.7
5.1
5.2
5.7
5.7
6.2
6.5
7.1
10.9
11.9
ns
ns
Table 1-36 • A42MX24 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T
J
= 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Parameter / Description Min. Max. Min. Max. Min. Max. Min. Ma x. Min. Max. Units
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold ti mi ng parame ters must acc ount fo r de lay fr om an extern al PAD sig nal to the G inpu ts . Dela y from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
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