40MX and 42MX FPGA Families
1-62 Revision 11
TTL Output Module Timing
5
t
DLH
Data-to-Pad HIGH 2.5 2.8 3.2 3.7 5.2 ns
t
DHL
Data-to-Pad LOW 3.0 3.3 3.7 4.4 6.1 ns
t
ENZH
Enable Pad Z to HIGH 2.7 3.0 3.4 4.0 5.6 ns
t
ENZL
Enable Pad Z to LOW 3.0 3.3 3.8 4.4 6.2 ns
t
ENHZ
Enable Pad HIGH to Z 5.4 6.0 6.8 8.0 11.2 ns
t
ENLZ
Enable Pad LOW to Z 5.0 5.6 6.3 7.4 10.4 ns
t
GLH
G-to-Pad HIGH 2.9 3.2 3.6 4.3 6.0 ns
t
GHL
G-to-Pad LOW 2.9 3.2 3.6 4.3 6.0 ns
t
LCO
I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
5.7 6.3 7.1 8.4 11.9 ns
t
ACO
Array Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
8.0 8.9 10.1 11.9 16.7 ns
d
TLH
Capacitive Loading, LOW to HIGH 0.03 0.03 0.03 0.04 0.06 ns/pF
d
THL
Capacitive Loading, HI GH to LOW 0.04 0.04 0.04 0.05 0.07 ns/pF
Table 1-34 • A42MX16 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T
J
= 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsParameter / Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, point and position whichever is
appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timi ng pa ra mete rs for the i npu t bu ff er latch ar e defin ed wit h resp ect to the PAD and the D inpu t. Ext erna l
setup/hold timing parameters must accoun t fo r delay f rom an exte rnal PAD signal to the G input s. Del ay from an externa l
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
