40MX and 42MX FPGA Families
1-58 Revision 11
TTL Output Module Timing
5
t
DLH
Data-to-Pad HIGH 3.4 3.8 4.3 5.1 7.1 ns
t
DHL
Data-to-Pad LOW 4.0 4.5 5.1 6.1 8.3 ns
t
ENZH
Enable Pad Z to HIGH 3.7 4.1 4.6 5.5 7.6 ns
t
ENZL
Enable Pad Z to LOW 4.1 4.5 5.1 6.1 8.5 ns
t
ENHZ
Enable Pad HIGH to Z 6.9 7.6 8.6 10.2 14.2 ns
t
ENLZ
Enable Pad LOW to Z 7.5 8.3 9.4 11.1 15.5 ns
t
GLH
G-to-Pad HIGH 5.8 6.5 7.3 8.6 12.0 ns
t
GHL
G-to-Pad LOW 5.8 6.5 7.3 8.6 12.0 ns
t
LSU
I/O Latch Set-Up 0.7 0.8 0.9 1.0 1.4 ns
t
LH
I/O Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
t
LCO
I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
8.7 9.7 10.9 12.9 18.0 ns
t
ACO
Array Clock-to-Out
(Pad-to-Pad),64 Clock Loading
12.2 13.5 15.4 18.1 25.3 ns
d
TLH
Capacity Loading, LOW to HIGH 0.00 0.00 0.00 0.10 0.01 ns/pF
d
THL
Capacity Loading, HIGH to LOW 0.09 0.10 0.10 0.10 0.10 ns/pF
Table 1-33 • A42MX09 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, T
J
= 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsParameter / Description Min. Max. Min. Max. Min . Max. Min. Max. Min. Ma x.
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for th e input buff er latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal t o the G inputs. Delay from an exte rnal
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.