40MX and 42MX FPGA Families
Revision 11 1-55
CMOS Output Module Timing
5
t
DLH
Data-to-Pad HIGH 2.4 2.7 3.1 3.6 5.1 ns
t
DHL
Data-to-Pad LOW 2.9 3.2 3.6 4.3 6.0 ns
t
ENZH
Enable Pad Z to HIGH 2.7 2.9 3.3 3.9 5.5 ns
t
ENZL
Enable Pad Z to LOW 2.9 3.2 3.7 4.3 6.1 ns
t
ENHZ
Enable Pad HI GH to Z 4.9 5.4 6.2 7.3 10.2 ns
t
ENLZ
Enable Pad LO W to Z 5.3 5.9 6.7 7.9 11.1 ns
t
GLH
G-to-Pad HIGH 4.2 4.6 5.2 6.1 8.6 ns
t
GHL
G-to-Pad LOW 4.2 4.6 5.2 6.1 8.6 ns
t
LSU
I/O Latch Set-Up 0.5 0.5 0.6 0.7 1.0 ns
t
LH
I/O Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
t
LCO
I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
5.2 5.8 6.6 7.7 10.8 ns
t
ACO
Array Clock-to-Out (
Pad-to-Pad), 64 Clock Loading
7.4 8.2 9.3 10.9 15.3 ns
d
TLH
Capacity Loading, LOW to HIGH 0.03 0.03 0.03 0.04 0.06 ns/pF
d
THL
Capacity Loading, HIGH to LOW 0.04 0.04 0.04 0.05 0.07 ns/pF
Table 1-32 • A42MX09 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T
J
= 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsParameter / Description Min. Max. Min. Max. Min . Max. Min. Max. Min. Max .
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hol d ti min g p arameters for th e i nput buf f er lat ch a re d efi ned with respe ct to the PAD an d the D i nput . Exte rnal
setup/hold timing parameters must acco unt f or delay from an e xtern al PAD signal to the G inputs . Delay from an exte rnal
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.