40MX and 42MX FPGA Families
1-52 Revision 11
Table 1-32 • A42MX09 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T
J
= 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsParameter / Description Min. Max. Min. Max. Min . Max. Min. Max. Min. Max .
Logic Module Propagation Delays
1
t
PD1
Single Module 1.2 1.3 1.5 1.8 2.5 ns
t
CO
Sequential Clock-to-Q 1.3 1.4 1.6 1.9 2.7 ns
t
GO
Latch G-to-Q 1.2 1.4 1.6 1.8 2.6 ns
t
RS
Flip-Flop (Latch) Reset-to-Q 1.2 1.6 1.8 2.1 2.9 n s
Logic Module Predicted Routing Delays2
t
RD1
FO = 1 Routing Delay 0.7 0.8 0.9 1.0 1.4 ns
t
RD2
FO = 2 Routing Delay 0.9 1.0 1.2 1.4 1.9 ns
t
RD3
FO = 3 Routing Delay 1.2 1.3 1.5 1.7 2.4 ns
t
RD4
FO = 4 Routing Delay 1.4 1.5 1.7 2.0 2.9 ns
t
RD8
FO = 8 Routing Delay 2.3 2.6 2.9 3.4 4.8 ns
Logic Module Sequential Timing3, 4
t
SUD
Flip-Flop (Latch)
Data Input Set-Up
0.3 0.4 0.4 0.5 0.7 ns
t
HD
Flip-Flop (Latch) Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns
t
SUENA
Flip-Flop (Latch) Enable Set-Up 0.4 0.5 0.5 0.6 0.8 ns
t
HENA
Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 0.0 ns
t
WCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
3.4 3.8 4.3 5.0 7.0 ns
t
WASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
4.5 4.9 5.6 6.6 9.2 ns
t
A
Flip-Flop Clock Input Period 3.5 3.8 4.3 5.1 7.1 ns
t
INH
Input Buffer Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
t
INSU
Input Buffer Latch Set-Up 0.3 0.3 0.4 0.4 0.6 ns
t
OUTH
Output Buffer Latch Hold 0.0 0.0 0.0 0.0 0.0 ns
t
OUTSU
Output Buffer Latch Set-U p 0.3 0.3 0.4 0.4 0.6 ns
f
MAX
Flip-Flop (Latch) Clock Frequency 268 244 224 195 117 MHz
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hol d ti min g p arameters for th e i nput buf f er lat ch a re d efi ned with respe ct to the PAD an d the D i nput . Exte rnal
setup/hold timing parameters must acco unt f or delay from an e xtern al PAD signal to the G inputs . Delay from an exte rnal
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
