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A40MX02-BGG208

A40MX02-BGG208首页预览图
型号: A40MX02-BGG208
PDF文件:
  • A40MX02-BGG208 PDF文件
  • A40MX02-BGG208 PDF在线浏览
功能描述: 40MX and 42MX FPGA Families
PDF文件大小: 7439.21 Kbytes
PDF页数: 共142页
制造商: MICROSEMI[Microsemi Corporation]
制造商LOGO: MICROSEMI[Microsemi Corporation] LOGO
制造商网址: http://www.microsemi.com
捡单宝A40MX02-BGG208
PDF页面索引
120%
40MX and 42MX FPGA Families
1-50 Revision 11
Input Module Predicted Rout ing Delays1
t
IRD1
FO = 1 Routing Delay 2.9 3.3 3.8 4.5 6.3 ns
t
IRD2
FO = 2 Routing Delay 3.6 4.2 4.8 5.6 7.8 ns
t
IRD3
FO = 3 Routing Delay 4.4 5.0 5.7 6.7 9.4 ns
t
IRD4
FO = 4 Routing Delay 5.1 5.9 6.7 7.8 11.0 ns
t
IRD8
FO = 8 Routing Delay 8.0 9.3 10.5 12.4 17.2 ns
Global Clock Network
t
CKH
Input LOW to HIGH FO = 16
FO = 128
6.4
6.4
7.4
7.4
8.4
8.4
9.9
9.9
13.8
13.8
ns
t
CKL
Input HIGH to LOW FO = 16
FO = 128
6.8
6.8
7.8
7.8
8.9
8.9
10.4
10.4
14.6
14.6
ns
t
PWH
Minimum Pulse
Width HIGH
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
ns
t
PWL
Minimum Pulse
Width LOW
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
ns
t
CKSW
Maximum Skew FO = 16
FO = 128
0.6
0.8
0.6
0.9
0.7
1.0
0.8
1.2
1.2
1.6
ns
t
P
Minimum Period FO = 16
FO = 128
6.5
6.8
7.5
7.8
8.5
8.9
10.1
10.4
14.1
14.6
ns
f
MAX
Maximum Frequency FO = 16
FO = 128
113
109
105
101
96
92
83
80
50
48
MHz
TTL Output Module Timing
4
t
DLH
Data-to-Pad HIGH 4.7 5.4 6.1 7.2 10.0 ns
t
DHL
Data-to-Pad LOW 5.6 6.4 7.3 8.6 12.0 ns
t
ENZH
Enable Pad Z to HIGH 5.2 6.0 6.9 8.1 11.3 ns
t
ENZL
Enable Pad Z to LOW 6.6 7.6 8.6 10.1 14.1 ns
t
ENHZ
Enable Pad HIGH to Z 11.1 12.8 14.5 17.1 23.9 ns
t
ENLZ
Enable Pad LOW to Z 8.2 9.5 10.7 12.6 17.7 ns
d
TLH
Delta LOW to HIGH 0.03 0.03 0.04 0.04 0.06 ns/pF
d
THL
Delta HIGH to LOW 0.04 0.04 0.05 0.06 0.08 ns/pF
Table 1-31 • A40MX04 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 3.0 V, T
J
= 70°C)
–3 Speed –2 Speed –1 Speed Std Sp eed –F Speed
UnitsParame ter / Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for th is ma cro.
4. Delays based on 35 pF loading.
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