40MX and 42MX FPGA Families
1-46 Revision 11
Table 1-30 • A40MX04 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCC = 4.75 V, T
J
= 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsParameter / Description Min . Max. Min. Max. Min. Max. Min. Max. Min. Max.
Logic Module Propagation Delays
t
PD1
Single Module 1.2 1.4 1.6 1.9 2.7 ns
t
PD2
Dual-Module Macros 2.3 3.1 3.5 4.1 5.7 ns
t
CO
Sequential Clock-to-Q 1.2 1.4 1.6 1.9 2.7 ns
t
GO
Latch G-to-Q 1.2 1.4 1.6 1.9 2.7 ns
t
RS
Flip-Flop (Latch) Reset-to-Q 1.2 1.4 1.6 1.9 2.7 ns
Logic Module Predicted Routing Delays1
t
RD1
FO = 1 Routing Delay 1.2 1.6 1.8 2.1 3.0 ns
t
RD2
FO = 2 Routing Delay 1.9 2.2 2.5 2.9 4.1 ns
t
RD3
FO = 3 Routing Delay 2.4 2.8 3.2 3.7 5.2 ns
t
RD4
FO = 4 Routing Delay 2.9 3.4 3.9 4.5 6.3 ns
t
RD8
FO = 8 Routing Delay 5.0 5.8 6.6 7.8 10.9 ns
Logic Module Sequential Timing2
t
SUD
Flip-Flop (Latch)
Data Input Set-Up
3.1 3.5 4.0 4.7 6.6 ns
t
HD
3
Flip-Flop (Latch)
Data Input Hold
0.0 0.0 0.0 0.0 0.0 ns
t
SUENA
Flip-Flop (Latch)
Enable Set-Up
3.1 3.5 4.0 4.7 6.6 ns
t
HENA
Flip-Flop (Latch)
Enable Hold
0.0 0.0 0.0 0.0 0.0 ns
t
WCLKA
Flip-Flop (Latch)
Clock Active Pulse Width
3.3 3.8 4.3 5.0 7.0 ns
t
WASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
3.3 3.8 4.3 5.0 7.0 ns
t
A
Flip-Flop Clo ck In pu t Pe riod 4.8 5.6 6.3 7.5 10.4 ns
f
MAX
Flip-Flop (Latch)
Clock Frequency
(FO = 128)
181 167 154 134 80 MHz
Input Modul e Pr opagation Del ays
t
INYH
Pad-to-Y HIGH 0.7 0.8 0.9 1.1 1.5 ns
t
INYL
Pad-to-Y LOW 0.6 0.7 0.8 1.0 1.3 ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to dete rmine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to
check the hold time for this macro.
4. Delays based on 35 pF loading.