40MX and 42MX FPGA Families
1-42 Revision 11
TTL Output Module Timing
4
t
DLH
Data-to-Pad HIGH 3.3 3.8 4.3 5.1 7.2 ns
t
DHL
Data-to-Pad LOW 4.0 4.6 5.2 6.1 8.6 ns
t
ENZH
Enable Pad Z to HIGH 3.7 4.3 4.9 5.8 8.0 ns
t
ENZL
Enable Pad Z to LOW 4.7 5.4 6.1 7.2 10.1 ns
t
ENHZ
Enable Pad HIGH to Z 7.9 9.1 10.4 12.2 17.1 ns
t
ENLZ
Enable Pad LOW to Z 5.9 6.8 7.7 9.0 12.6 n s
d
TLH
Delta LOW to HIGH 0.02 0.02 0.03 0.03 0.04 ns/pF
d
THL
Delta HIGH to LOW 0.03 0.03 0.03 0.04 0.06 ns/pF
CMOS Output Mo dule Timing
4
t
DLH
Data-to-Pad HIGH 3.9 4.5 5.1 6.05 8.5 ns
t
DHL
Data-to-Pad LOW 3.4 3.9 4.4 5.2 7.3 ns
t
ENZH
Enable Pad Z to HIGH 3.4 3.9 4.4 5.2 7.3 ns
t
ENZL
Enable Pad Z to LOW 4.9 5.6 6.4 7.5 10.5 ns
t
ENHZ
Enable Pad HIGH to Z 7.9 9.1 10.4 12.2 17.0 ns
t
ENLZ
Enable Pad LOW to Z 5.9 6.8 7.7 9.0 12.6 n s
d
TLH
Delta LOW to HIGH 0.03 0.04 0.04 0.05 0.07 ns/pF
d
THL
Delta HIGH to LOW 0.02 0.02 0.03 0.03 0.04 ns/pF
Table 1-28 • A40MX02 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 4.75 V, T
J
= 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsParameter / Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for th is ma cro.
4. Delays based on 35pF loading.
