40MX and 42MX FPGA Families
Revision 11 1-41
Input Module Predicted Routing Delays
1
t
IRD1
FO = 1 Routing Delay 2.1 2.4 2.2 3.2 4.5 ns
t
IRD2
FO = 2 Routing Delay 2.6 3.0 3.4 4.0 5.6 ns
t
IRD3
FO = 3 Routing Delay 3.1 3.6 4.1 4.8 6.7 ns
t
IRD4
FO = 4 Routing Delay 3.6 4.2 4.8 5.6 7.8 ns
t
IRD8
FO = 8 Routing Delay 5.7 6.6 7.5 8.8 12.4 ns
Global Clock Network
t
CKH
Input Low to HIGH FO = 16
FO = 128
4.6
4.6
5.3
5.3
6.0
6.0
7.0
7.0
9.8
9.8
ns
t
CKL
Input High to LOW FO = 16
FO = 128
4.8
4.8
5.6
5.6
6.3
6.3
7.4
7.4
10.4
10.4
ns
t
PWH
Minimum Pulse
Width HIGH
FO = 16
FO = 128
2.2
2.4
2.6
2.7
2.9
3.1
3.4
3.6
4.8
5.1
ns
t
PWL
Minimum Pulse
Width LOW
FO = 16
FO = 128
2.2
2.4
2.6
2.7
2.9
3.01
3.4
3.6
4.8
5.1
ns
t
CKSW
Maximum Skew FO = 16
FO = 128
0.4
0.5
0.5
0.6
0.5
0.7
0.6
0.8
0.8
1.2
ns
t
P
Minimum Period FO = 16
FO = 128
4.7
4.8
5.4
5.6
6.1
6.3
7.2
7.5
10.0
10.4
ns
f
MAX
Maximum
Frequency
FO = 16
FO = 128
188
181
175
168
160
154
139
134
83
80
MHz
Table 1-28 • A40MX02 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 4.75 V, T
J
= 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
UnitsParameter / Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for th is ma cro.
4. Delays based on 35pF loading.