40MX and 42MX FPGA Families
1-34 Revision 11
Note: Identical timing for fa llin g edge clock.
Figure 1- 30 • 42MX SRAM Synchronous Read Operation
Figure 1- 31 • 42MX SRAM Asynchronous Read Operation—Type 1 (Read Address Controlled)
Figure 1- 32 • 42MX SRAM Asynchronous Read Operation—Type 2 (Write Address Controlled)
RCLK
REN
RDAD[5:0]
RD[7:0]
Old Data
Valid
t
RCKHL
t
CKHL
t
RENH
t
RCO
t
ADH
t
DOH
t
ADSU
New Data
t
RENSU
RDAD[5:0]
RD[7:0]
Data 1
t
RDADV
t
DOH
ADDR2ADDR1
Data 2
t
RPD
WEN
WD[7:0]
WCLK
RD[7:0]
Old Data
Valid
t
WENH
t
RPD
t
WENSU
New Data
t
DOH
tADSU
WRAD[5:0]
BLKEN
t
ADH