40MX and 42MX FPGA Families
Revision 11 1-33
Decode Module Timing
SRAM Timing Characteristics
Dual-Port SRAM Timing Waveforms
Figure 1- 27 • Decode Module Timing
Figure 1- 28 • SRAM Timing Characteristics
Note: Identical timing for fall ing ed ge clock.
Figure 1- 29 • 42MX SRAM Write Operation
A–G, H
Y
t
PLH
50%
t
PHL
Y
A
B
C
D
E
F
G
H
WRAD [5:0]
BLKEN
WEN
WCLK
RDA D [5 :0 ]
LEW
REN
RCLK
RD [7:0]
WD [7:0]
Write Port
Read Port
RAM Array
3 2x8 or 64x4
(2 56 Bits)
WCLK
WD[7:0]
WRAD[5:0]
WEN
BLKEN
Valid
Valid
t
RCKHL
t
RCKHL
t
WENSU
t
BENSU
t
WENH
t
BENH
t
ADSU
t
ADH
