40MX and 42MX FPGA Families
Revision 11 1-31
Sequential Module Timing Characteristics
Figure 1- 23 • Module Delays
Note: *D represents all data functions involving A, B, and S for multiplexed flip-flo ps.
Figure 1- 24 • Flip-Flops and Latches
S
A
B
Y
S, A or B
Y
50%
t
PLH
Y
50%
50%
50%
50%
50%
t
PHL
PHL
t
PLH
t
WCLKA
t
WASYN
t
HD
t
SUENA
t
SUD
t
RS
t
A
t
WCLK1
t
CO
t
HENA
D*
G, CLK
E
Q
PRE, CLR
(Positive Edge-Triggered)
D
E
CLK
CLR
PRE
Y