40MX and 42MX FPGA Families
1-28 Revision 11
Notes:
1. Load-dependent
2. Values are shown for A42MX36 –3 at 5.0 V worst-case commercial conditions.
Figure 1-18 • 42MX Timing Model (Logi c Functions Using Quadrant Clocks)
t
SUD
= 3.0 ns
t
HD
= 0.0 ns
F
MAX
=180 MHz
t
CKH
=3.03 ns
1
Quadrant
Clocks
t
CO
= 1.3 ns
t
RD1
= 0.9 ns
Sequential
Logic Module
t
LH
= 0.00 ns
t
LSU
= 0.5 ns
t
GHL
= 2.9 ns
t
ENHZ
= 5.3 ns
t
DLH
= 2.6 ns
t
RDD
= 0.3 ns
t
PDD
= 1.6 ns
t
INH
= 0.0 ns
t
INSU
= 0.5 ns
t
INGO
= 1.4 ns
t
RD1
= 0.9 ns
t
RD2
= 1.3 ns
t
RD4
= 2.0 ns
t
DLH
= 2.6 ns
t
PD
=1.3 ns
t
INPY
= 1.0 ns
t
IRD1
= 2.0 ns
I/O Module
Combinatorial
Module
I/O Module
Decode
Module
Comb.
Logic
Include
D
Q
DQ
G
G
D
Q
I/O Module
Input Delays
Internal Delays
Output Delays
Predicted
Routing
Delays