40MX and 42MX FPGA Families
Revision 11 1-27
Timing Models
Note: Values are shown for 40MX –3 speed devices at 5.0 V worst-case commercial condi tions.
Figure 1-16 • 40MX Timing Model*
Notes:
1. Input module predict ed routing delay
2. Values are shown for A42MX09 –3 at 5.0 V worst-case commercial conditions.
Figure 1-17 • 42MX Timing Model
Output DelayInput Delay
Logic Module
Internal Delays
t
DLH
= 3.32 ns
t
ENHZ
= 7.92 ns
t
RD1
= 1.28 ns
t
RD2
= 1.80 ns
t
RD4
= 2.33 ns
t
RD8
= 4.93 ns
I/O Module
t
PD
= 1.24 ns
t
CO
= 1.24 ns
t
IRD1
= 2.09 ns
t
IRD4
= 3.64 ns
t
IRD8
= 5.73 ns
t
INYL
= 0.62 ns
t
IRD2
= 2.59 ns
I/O Module
F
MAX
= 180 MHz
t
CKH
= 4.55 ns
FO = 128
Array
Clock
Predicted
Routing
Delays
Array
Clocks
Comb.
Logic
Include
DQ
FO = 3 2
Ou tp ut Del aysIn tern al Del aysI np ut Del ays
I /O Module
DQ
Combinatorial
Logic Module
Sequential
Logic Module
I /O Module
I /O Module
DQ
Predicted
Routing
Delays
G
G
t
RD1
= 0.7 ns
t
RD2
= 1.9 ns
t
RD4
= 1.4 ns
t
RD8
= 2.3 ns
t
OUTH
= 0.00 ns
t
OUTSU
= 0.3 ns
t
GLH
= 2.6 ns
t
DLH
= 2.5 ns
t
DLH
= 2.5 ns
t
ENHZ
= 4.9 ns
t
RD1
= 0.70 ns
t
LCO
= 5.2 ns (light loads, pad-to-pad)
t
CO = 1.3 ns
t
SUD
= 0.3 ns
t
HD
= 0.00 ns
t
PD
=1.2 ns
t
IRD1
= 2.0 ns
1
t
INYL
= 0.8 ns
t
I
NH
= 0.0 ns
t
INSU
= 0.3 ns
t
INGL
= 1.3 ns
F
MAX
= 296 MHz
t
CKH
= 2.70 ns