40MX and 42MX FPGA Families
Revision 11 1-23
Output Drive Characteristics for 5.0 V PCI Signaling
MX PCI device I/O drivers were designed specifically for high-performance PC I systems. F igure 1-15 on
page 1-25 shows the typical output drive characteristics of the MX devices. MX output drivers are
compliant with the PCI Local Bus S pecification.
Table 1-17 • DC Specification (5.0 V PCI Signaling)
1
PCI MX
Symbol Parameter Condition Min. Max. Min. Max. Units
VCCI Supply Voltage for I/Os 4.75 5.25 4.75 5.25
2
V
VIH Input High Voltage 2.0 VCC + 0.5 2.0 VCCI + 0.3 V
VIL Input Low Voltage –0.5 0.8 –0.3 0.8 V
IIH Input High Leakage Current VIN = 2.7 V 70 — 10 µA
IIL Input Low Leakage Cu rrent VIN=0.5 V –70 — –10 µA
VOH Output High Voltage IOUT = –2 mA
IOUT = –6 mA
2.4
3.84
V
VOL Output Low Voltage IOUT = 3 mA, 6 mA 0.55 — 0.33 V
C
IN
Input Pin Capacitance 10 — 10 pF
C
CLK
CLK Pin Capacitance 5 12 — 10 pF
L
PIN
Pin Inductance 20 — < 8 nH
3
nH
Notes:
1. PCI Local Bus Specification, Version 2.1, Section 4.2.1.1.
2. Maximum rating for VCCI –0.5 V to 7.0V.
3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and
capacitance.
Table 1-18 • AC Specifications (5.0V PCI Signaling)
*
PCI MX
Symbol Parameter Condition Min. Max. Min. Max. Units
ICL Low Clamp Current –5 < VIN ≤ –1 –25 + (VIN +1) /0.015 –60 –10 mA
Slew (r) Output Rise Slew Rate 0.4 V to 2.4 V load 1 5 1.8 2.8 V/ns
Slew (f) Output Fall Slew Rate 2.4 V to 0.4 V load 1 5 2.8 4.3 V/ns
Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.1.2.
