40MX and 42MX FPGA Families
Revision 11 1-11
C
EQ
Values for Microsemi MX FPGAs
Modules (C
EQM
)3.5
Input Buffers (C
EQI
)6.9
Output Buffers (C
EQO
)18.2
Routed Array Clock Buffer Loads (C
EQCR
)1.4
To calculate the active power dissipated from the complete design, the switching freq uency of each part
of the logic must be known. The equation below shows a piece-wise linear summation over all
components.
Power = VCCA
2
* [(m x C
EQM
* f
m
)
Modules
+
(n * C
EQI
* f
n
)
Inputs
+ (p * (C
EQO
+ C
L
) * f
p
)
outputs
+
0.5 * (q
1
* C
EQCR
* f
q1
)
routed_Clk1
+ (r
1
* f
q1
)
routed_Clk1
+
0.5 * (q
2
* C
EQCR
* f
q2
)
routed_Clk2
+ (r
2
* f
q2
)
routed_Clk2
(2)
where:
Fixed Capacitance Values for MX FPGAs (pF)
m = Number of logic modules switching at frequency f
m
n = Number of input buffers switching at frequency f
n
p = Number of output buffers switching at frequency f
p
q
1
= Number of clock loads on the first routed array clock
q
2
= Number of clock loads on the second routed array clock
r
1
= Fixed capacitance due to first routed array clock
r
2
= Fixed capacitance due to second routed array clock
C
EQM
= Equivalent capacitance of logic mo dules in pF
C
EQI
= Equivalent capacitance of input buffers in pF
C
EQO
= Equivalent capacitance of outp ut buffers in pF
C
EQC
R
= Equivalent capacitance of routed array clock in pF
C
L
= Output load capacitance in pF
f
m
= Average logic module switching rate in MHz
f
n
= A verage input buffer switching rate in MHz
f
p
= Average output buffer switching rate in MHz
f
q1
= Average first routed array clock rate in MHz
f
q2
= A verage second routed array clock rate in MHz
Device Type
r1
routed_Clk1
r2
routed_Clk2
A40MX02 41.4 N/A
A40MX04 68.6 N/A
A42MX09 118 118
A42MX16 165 165
A42MX24 185 185
A42MX36 220 220
