ProASIC3 Flash Family FPGAs
Revision 13 2-53
Table 2-68 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
1.8 V
LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL
1
IIH
2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmAmA
Max.
mA
3
Max.
mA
3
µA
4
µA
4
2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 2 2 9 11 10 10
4 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4 17 22 10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Figure 2-8 • AC Loading
Table 2-69 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V) Measuring Point* (V) C
LOAD
(pF)
01.80.935
Note: *Measuring point = Vtrip
.
See Table 2-22 on page 2-21 for a complete table of trip points.
Test Point
Test Point
Enable Path
Datapath
35 pF
R = 1 k
R to VCCI for t
LZ
/ t
ZL
/ t
ZLS
R to GND for t
HZ
/ t
ZH
/ t
ZHS
35 pF for t
ZH
/ t
ZHS
/ t
ZL
/ t
ZLS
35 pF for t
HZ
/ t
LZ