ProASIC3 Flash Family FPGAs
Revision 13 2-37
Table 2-46 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial-Case Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard I/O Banks
Drive
Strength
Speed
Grade t
DOUT
t
DP
t
DIN
t
PY
t
EOUT
t
ZL
t
ZH
t
LZ
t
HZ
Units
2 mA Std. 0.66 9.46 0.04 1.00 0.43 9.64 8.54 2.07 2.04 ns
–1 0.56 8.05 0.04 0.85 0.36 8.20 7.27 1.76 1.73 ns
–2 0.49 7.07 0.03 0.75 0.32 7.20 6.38 1.55 1.52 ns
4 mA Std. 0.66 9.46 0.04 1.00 0.43 9.64 8.54 2.07 2.04 ns
–1 0.56 8.05 0.04 0.85 0.36 8.20 7.27 1.76 1.73 ns
–2 0.49 7.07 0.03 0.75 0.32 7.20 6.38 1.55 1.52 ns
6 mA Std. 0.66 6.57 0.04 1.00 0.43 6.69 5.98 2.40 2.57 ns
–1 0.56 5.59 0.04 0.85 0.36 5.69 5.09 2.04 2.19 ns
–2 0.49 4.91 0.03 0.75 0.32 5.00 4.47 1.79 1.92 ns
8 mA Std. 0.66 6.57 0.04 1.00 0.43 6.69 5.98 2.40 2.57 ns
–1 0.56 5.59 0.04 0.85 0.36 5.69 5.09 2.04 2.19 ns
–2 0.49 4.91 0.03 0.75 0.32 5.00 4.47 1.79 1.92 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.