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A3P250-2TQ144PP

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型号: A3P250-2TQ144PP
PDF文件:
  • A3P250-2TQ144PP PDF文件
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功能描述: ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
PDF文件大小: 10669.38 Kbytes
PDF页数: 共220页
制造商: MICROSEMI[Microsemi Corporation]
制造商LOGO: MICROSEMI[Microsemi Corporation] LOGO
制造商网址: http://www.microsemi.com
捡单宝A3P250-2TQ144PP
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120%
ProASIC3 DC and Switching Characteristics
2-30 Revision 13
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The
reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 100°C, the short current condition would have to be sustained for more than six months
to cause a reliability concern. The I/O design does not contain any short circuit protection, but such
protection would only be needed in extremely prolonged stress conditions.
Table 2-34 • I/O Short Currents IOSH/IOSL
Applicable to Standard I/O Banks
Drive Strength IOSL (mA)* IOSH (mA)*
3.3 V LVTTL / 3.3 V LVCMOS 2 mA 27 25
4 mA 27 25
6 mA 54 51
8 mA 54 51
3.3 V LVCMOS Wide Range
2
100 µA Same as regular
3.3 V LVCMOS
Same as regular
3.3 V LVCMOS
2.5 V LVCMOS 2 mA 18 16
4 mA 18 16
6 mA 37 32
8 mA 37 32
1.8 V LVCMOS 2 mA 11 9
4 mA 22 17
1.5 V LVCMOS 2 mA 16 13
Notes:
1. T
J
= 100°C
2. Applicable to 3.3 V LVCMOS Wide Range. I
OSL
/I
OSH
dependent on the I/O buffer drive strength selected
for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as
specified in the JESD-8B specification.
Table 2-35 • Duration of Short Circuit Event Before Failure
Temperature Time before Failure
–40°C > 20 years
0°C > 20 years
25°C > 20 years
70°C 5 years
85°C 2 years
100°C 6 months
Table 2-36 • I/O Input Rise Time, Fall Time, and Related I/O Reliability
Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability
LVTTL/LVCMOS No requirement 10 ns * 20 years (110°C)
LVDS/B-LVDS/
M-LVDS/LVPECL
No requirement 10 ns * 10 years (100°C)
Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the
noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum
value. The longer the rise/fall times, the more susceptible the input signal is to the board noise.
Microsemi recommends signal integrity evaluation/characterization of the system to ensure that
there is no excessive noise coupling into input signals.
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