ProASIC3 Flash Family FPGAs
Revision 13 2-13
RAM Contribution—P
MEMORY
P
MEMORY
= P
AC11
* N
BLOCKS
* F
READ-CLOCK
*
2
+ P
AC12
* N
BLOCK
* F
WRITE-CLOCK
*
3
N
BLOCKS
is the number of RAM blocks used in the design.
F
READ-CLOCK
is the memory read clock frequency.
2
is the RAM enable rate for read operations.
F
WRITE-CLOCK
is the memory write clock frequency.
3
is the RAM enable rate for write operations—guidelines are provided in Table 2-17 on page 2-13.
PLL Contribution—P
PLL
P
PLL
= P
DC4
+ P
AC13
*F
CLKOUT
F
CLKOUT
is the output clock frequency.
1
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are
some examples:
• The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the
clock frequency.
• The average toggle rate of an 8-bit counter is 25%:
– Bit 0 (LSB) = 100%
– Bit 1 = 50%
– Bit 2 = 25%
–…
– Bit 7 (MSB) = 0.78125%
– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
nontristate output buffers are used, the enable rate should be 100%.
1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula by adding its corresponding contribution (P
AC14
* F
CLKOUT
product) to the total PLL contribution.
Table 2-16 • Toggle Rate Guidelines Recommended for Power Calculation
Component Definition Guideline
1
Toggle rate of VersaTile outputs 10%
2
I/O buffer toggle rate 10%
Table 2-17 • Enable Rate Guidelines Recommended for Power Calculation
Component Definition Guideline
1
I/O output buffer enable rate 100%
2
RAM enable rate for read operations 12.5%
3
RAM enable rate for write operations 12.5%