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A3P250-2TQ144PP

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型号: A3P250-2TQ144PP
PDF文件:
  • A3P250-2TQ144PP PDF文件
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功能描述: ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
PDF文件大小: 10669.38 Kbytes
PDF页数: 共220页
制造商: MICROSEMI[Microsemi Corporation]
制造商LOGO: MICROSEMI[Microsemi Corporation] LOGO
制造商网址: http://www.microsemi.com
捡单宝A3P250-2TQ144PP
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ProASIC3 Flash Family FPGAs
Revision 13 2-11
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in Libero SoC software.
The power calculation methodology described below uses the following variables:
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-16 on
page 2-13.
Enable rates of output buffers—guidelines are provided for typical applications in Table 2-17 on
page 2-13.
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-17 on page 2-13. The calculation should be repeated for each clock domain defined in the
design.
Methodology
Total Power Consumption—P
TOTAL
P
TOTAL
= P
STAT
+ P
DYN
P
STAT
is the total static power consumption.
P
DYN
is the total dynamic power consumption.
Total Static Power Consumption—P
STAT
P
STAT
= P
DC1
+ N
INPUTS
* P
DC2
+ N
OUTPUTS
* P
DC3
N
INPUTS
is the number of I/O input buffers used in the design.
N
OUTPUTS
is the number of I/O output buffers used in the design.
Table 2-15 • Different Components Contributing to the Static Power Consumption in ProASIC3 Devices
Parameter
Definition Device Specific Static Power (mW)
A3P1000
A3P600
A3P400
A3P250
A3P125
A3P060
A3P030
A3P015
PDC1 Array static power in Active mode See Table 2-7 on page 2-6.
PDC2 I/O input pin static power (standard-dependent) See Table 2-8 on page 2-6 through
Table 2-10 on page 2-7.
PDC3 I/O output pin static power (standard-dependent) See Table 2-11 on page 2-8 through
Table 2-13 on page 2-9.
PDC4 Static PLL contribution 2.55 mW
PDC5 Bank quiescent power (VCCI-dependent) See Table 2-7 on page 2-6.
Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power
spreadsheet calculator or SmartPower tool in Libero SoC software.
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