ProASIC3 Flash Family FPGAs
Revision 13 2-7
Table 2-9 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings
Applicable to Standard Plus I/O Banks
VMV (V)
Static Power
PDC2 (mW)
1
Dynamic Power
PAC9 (µW/MHz)
2
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 16.23
3.3 V LVCMOS Wide Range
3
3.3 – 16.23
2.5 V LVCMOS 2.5 – 5.14
1.8 V LVCMOS 1.8 – 2.13
1.5 V LVCMOS (JESD8-11) 1.5 – 1.48
3.3 V PCI 3.3 – 18.13
3.3 V PCI-X 3.3 – 18.13
Notes:
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B
specification.
Table 2-10 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings
Applicable to Standard I/O Banks
VMV (V)
Static Power
PDC2
(mW)
1
Dynamic Power
PAC9 (µW/MHz)
2
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 17.24
3.3 V LVCMOS Wide Range
3
3.3 – 17.24
2.5 V LVCMOS 2.5 – 5.19
1.8 V LVCMOS 1.8 – 2.18
1.5 V LVCMOS (JESD8-11) 1.5 – 1.52
Notes:
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B
specification.