ProASIC3 Flash Family FPGAs
Revision 13 2-101
Timing Characteristics
Table 2-118 • FIFO (for all dies except A3P250)
Worst Commercial-Case Conditions: T
J
= 70°C, VCC = 1.425 V
Parameter Description –2 –1 Std. Units
t
ENS
REN, WEN Setup Time 1.34 1.52 1.79 ns
t
ENH
REN, WEN Hold Time 0.00 0.00 0.00 ns
t
BKS
BLK Setup Time 0.19 0.22 0.26 ns
t
BKH
BLK Hold Time 0.00 0.00 0.00 ns
t
DS
Input Data (WD) Setup Time 0.18 0.21 0.25 ns
t
DH
Input Data (WD) Hold Time 0.00 0.00 0.00 ns
t
CKQ1
Clock High to New Data Valid on RD (flow-through) 2.17 2.47 2.90 ns
t
CKQ2
Clock High to New Data Valid on RD (pipelined) 0.94 1.07 1.26 ns
t
RCKEF
RCLK High to Empty Flag Valid 1.72 1.96 2.30 ns
t
WCKFF
WCLK High to Full Flag Valid 1.63 1.86 2.18 ns
t
CKAF
Clock High to Almost Empty/Full Flag Valid 6.19 7.05 8.29 ns
t
RSTFG
RESET Low to Empty/Full Flag Valid 1.69 1.93 2.27 ns
t
RSTAF
RESET Low to Almost Empty/Full Flag Valid 6.13 6.98 8.20 ns
t
RSTBQ
RESET Low to Data Out Low on RD (flow-through) 0.92 1.05 1.23 ns
RESET Low to Data Out Low on RD (pipelined) 0.92 1.05 1.23 ns
t
REMRSTB
RESET Removal 0.29 0.33 0.38 ns
t
RECRSTB
RESET Recovery 1.50 1.71 2.01 ns
t
MPWRSTB
RESET Minimum Pulse Width 0.21 0.24 0.29 ns
t
CYC
Clock Cycle Time 3.23 3.68 4.32 ns
F
MAX
Maximum Frequency for FIFO 310 272 231 MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.