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A3P250-2TQ144PP

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型号: A3P250-2TQ144PP
PDF文件:
  • A3P250-2TQ144PP PDF文件
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功能描述: ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
PDF文件大小: 10669.38 Kbytes
PDF页数: 共220页
制造商: MICROSEMI[Microsemi Corporation]
制造商LOGO: MICROSEMI[Microsemi Corporation] LOGO
制造商网址: http://www.microsemi.com
捡单宝A3P250-2TQ144PP
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120%
ProASIC3 DC and Switching Characteristics
2-88 Revision 13
Table 2-113 • A3P600 Global Resource
Commercial-Case Conditions: T
J
= 70°C, VCC = 1.425 V
Parameter Description
–2 1 Std.
UnitsMin.
1
Max.
2
Min.
1
Max.
2
Min.
1
Max.
2
t
RCKL
Input Low Delay for Global Clock 0.87 1.09 0.99 1.24 1.17 1.46 ns
t
RCKH
Input High Delay for Global Clock 0.86 1.11 0.98 1.27 1.15 1.49 ns
t
RCKMPWH
Minimum Pulse Width High for Global Clock 0.75 0.85 1.00 ns
t
RCKMPWL
Minimum Pulse Width Low for Global Clock 0.85 0.96 1.13 ns
t
RCKSW
Maximum Skew for Global Clock 0.26 0.29 0.34 ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-114 • A3P1000 Global Resource
Commercial-Case Conditions: T
J
= 70°C, VCC = 1.425 V
Parameter Description
–2 –1 Std.
UnitsMin.
1
Max.
2
Min.
1
Max.
2
Min.
1
Max.
2
t
RCKL
Input Low Delay for Global Clock 0.94 1.16 1.07 1.32 1.26 1.55 ns
t
RCKH
Input High Delay for Global Clock 0.93 1.19 1.06 1.35 1.24 1.59 ns
t
RCKMPWH
Minimum Pulse Width High for Global Clock 0.75 0.85 1.00 ns
t
RCKMPWL
Minimum Pulse Width Low for Global Clock 0.85 0.96 1.13 ns
t
RCKSW
Maximum Skew for Global Clock 0.26 0.29 0.35 ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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