ProASIC3 Flash Family FPGAs
Revision 13 2-81
Figure 2-24 • Timing Model and Waveforms
t
PD
A
B
t
PD
= MAX(t
PD(RR)
, t
PD(RF)
, t
PD(FF)
, t
PD(FR)
)
where edges are applicable for the particular
combinatorial cell
Y
NAND2 or
Any Combinatorial
Logic
t
PD
t
PD
50%
VCC
VCC
VCC
50%
GND
A, B, C
50%
50%
50%
(RR)
(RF)
GND
OUT
OUT
GND
50%
(FF)
(FR)
t
PD
t
PD