ProASIC3 Flash Family FPGAs
Revision 13 2-79
Timing Characteristics
Figure 2-22 • Output DDR Timing Diagram
116
1
7
2
8
3
910
45
28 3 9
t
DDROREMCLR
t
DDROHD1
t
DDROREMCLR
t
DDROHD2
t
DDROSUD2
t
DDROCLKQ
t
DDRORECCLR
CLK
Data_R
Data_F
CLR
Out
t
DDROCLR2Q
7104
Table 2-104 • Output DDR Propagation Delays
Commercial-Case Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
Parameter Description –2 –1 Std. Units
t
DDROCLKQ
Clock-to-Out of DDR for Output DDR 0.70 0.80 0.94 ns
t
DDROSUD1
Data_F Data Setup for Output DDR 0.38 0.43 0.51 ns
t
DDROSUD2
Data_R Data Setup for Output DDR 0.38 0.43 0.51 ns
t
DDROHD1
Data_F Data Hold for Output DDR 0.00 0.00 0.00 ns
t
DDROHD2
Data_R Data Hold for Output DDR 0.00 0.00 0.00 ns
t
DDROCLR2Q
Asynchronous Clear-to-Out for Output DDR 0.80 0.91 1.07 ns
t
DDROREMCLR
Asynchronous Clear Removal Time for Output DDR 0.00 0.00 0.00 ns
t
DDRORECCLR
Asynchronous Clear Recovery Time for Output DDR 0.22 0.25 0.30 ns
t
DDROWCLR1
Asynchronous Clear Minimum Pulse Width for Output DDR 0.22 0.25 0.30 ns
t
DDROCKMPWH
Clock Minimum Pulse Width High for the Output DDR 0.36 0.41 0.48 ns
t
DDROCKMPWL
Clock Minimum Pulse Width Low for the Output DDR 0.32 0.37 0.43 ns
F
DDOMAX
Maximum Frequency for the Output DDR 350 309 263 MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.