ProASIC3 DC and Switching Characteristics
2-74 Revision 13
Output Enable Register
Figure 2-18 • Output Enable Register Timing Diagram
50%
Preset
Clear
EOUT
CLK
D_Enable
Enable
t
OESUE
50%
50%
t
OESUD
t
OEHD
50% 50%
t
OECLKQ
1
0
t
OEHE
t
OERECPRE
t
OEREMPRE
t
OERECCLR
t
OEREMCLR
t
OEWCLR
t
OEWPRE
t
OEPRE2Q
t
OECLR2Q
t
OECKMPWH
t
OECKMPWL
50% 50%
50% 50% 50%
50% 50%
50%
50%
50% 50%
50%
50%
50%