ProASIC3 Flash Family FPGAs
Revision 13 2-65
Timing Characteristics
Table 2-90 • LVDS Minimum and Maximum DC Input and Output Levels
DC Parameter Description Min. Typ. Max. Units
VCCI Supply Voltage 2.375 2.5 2.625 V
VOL Output Low Voltage 0.9 1.075 1.25 V
VOH Output High Voltage 1.25 1.425 1.6 V
IOL
1
Output Lower Current 0.65 0.91 1.16 mA
IOH
1
Output High Current 0.65 0.91 1.16 mA
VI Input Voltage 0 2.925 V
IIH
2,3
Input High Leakage Current 10 µA
IIL
2,4
Input Low Leakage Current 10 µA
VODIFF Differential Output Voltage 250 350 450 mV
VOCM Output Common Mode Voltage 1.125 1.25 1.375 V
VICM Input Common Mode Voltage 0.05 1.25 2.35 V
VIDIFF Input Differential Voltage 100 350 mV
Notes:
1. IOL/ IOH defined by VODIFF/(Resistor Network)
2. Currents are measured at 85°C junction temperature.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN <VCCI. Input current is
larger when operating outside recommended ranges.
4. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN <VIL.
Table 2-91 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V) Measuring Point* (V)
1.075 1.325 Cross point
Note: *Measuring point = V
trip.
See Table 2-22 on page 2-21 for a complete table of trip points.
Table 2-92 • LVDS
Commercial-Case Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Speed Grade t
DOUT
t
DP
t
DIN
t
PY
Units
Std. 0.66 1.83 0.04 1.60 ns
–1 0.56 1.56 0.04 1.36 ns
–2 0.49 1.37 0.03 1.20 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
