ProASIC3 Flash Family FPGAs
Revision 13 2-61
Table 2-81 • 1.5 V LVCMOS Low Slew
Commercial-Case Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Advanced I/O Banks
Drive
Strength
Speed
Grade t
DOUT
t
DP
t
DIN
t
PY
t
EOUT
t
ZL
t
ZH
t
LZ
t
HZ
t
ZLS
t
ZHS
Units
2 mA Std. 0.66 12.78 0.04 1.44 0.43 12.81 12.78 3.40 2.64 15.05 15.02 ns
–1 0.56 10.87 0.04 1.22 0.36 10.90 10.87 2.89 2.25 12.80 12.78 ns
–2 0.49 9.55 0.03 1.07 0.32 9.57 9.55 2.54 1.97 11.24 11.22 ns
4 mA Std. 0.66 10.01 0.04 1.44 0.43 10.19 9.55 3.75 3.27 12.43 11.78 ns
–1 0.56 8.51 0.04 1.22 0.36 8.67 8.12 3.19 2.78 10.57 10.02 ns
–2 0.49 7.47 0.03 1.07 0.32 7.61 7.13 2.80 2.44 9.28 8.80 ns
6 mA Std. 0.66 9.33 0.04 1.44 0.43 9.51 8.89 3.83 3.43 11.74 11.13 ns
–1 0.56 7.94 0.04 1.22 0.36 8.09 7.56 3.26 2.92 9.99 9.47 ns
–2 0.49 6.97 0.03 1.07 0.32 7.10 6.64 2.86 2.56 8.77 8.31 ns
8 mA Std. 0.66 8.91 0.04 1.44 0.43 9.07 8.89 3.95 4.05 11.31 11.13 ns
–1 0.56 7.58 0.04 1.22 0.36 7.72 7.57 3.36 3.44 9.62 9.47 ns
–2 0.49 6.65 0.03 1.07 0.32 6.78 6.64 2.95 3.02 8.45 8.31 ns
12 mA Std. 0.66 8.91 0.04 1.44 0.43 9.07 8.89 3.95 4.05 11.31 11.13 ns
–1 0.56 7.58 0.04 1.22 0.36 7.72 7.57 3.36 3.44 9.62 9.47 ns
–2 0.49 6.65 0.03 1.07 0.32 6.78 6.64 2.95 3.02 8.45 8.31 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.