ProASIC3 Flash Family FPGAs
Revision 13 2-27
Table 2-30 • I/O Output Buffer Maximum Resistances
1
Applicable to Standard I/O Banks
Standard Drive Strength
R
PULL-DOWN
()
2
R
PULL-UP
()
3
3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300
4 mA 100 300
6 mA 50 150
8 mA 50 150
3.3 V LVCMOS Wide Range
4
100 µA Same as regular
3.3 V LVCMOS
Same as regular
3.3 V LVCMOS
2.5 V LVCMOS 2 mA 100 200
4 mA 100 200
6 mA 50 100
8 mA 50 100
1.8 V LVCMOS 2 mA 200 225
4 mA 100 112
1.5 V LVCMOS 2 mA 200 224
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on VCCI, drive strength selection, temperature, and process. For board design
considerations and detailed output buffer resistances, use the corresponding IBIS models located at
http://www.microsemi.com/soc/download/ibis/default.aspx.
2. R
(PULL-DOWN-MAX)
= (VOLspec) / IOLspec
3. R
(PULL-UP-MAX)
= (VCCImax – VOHspec) / IOHspec
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B
specification.
Table 2-31 • I/O Weak Pull-Up/Pull-Down Resistances
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
VCCI
R
(WEAK PULL-UP)
1
()
R
(WEAK PULL-DOWN)
2
()
Min. Max. Min. Max.
3.3 V 10 k 45 k 10 k 45 k
3.3 V (wide range I/Os) 10 k 45 k 10 k 45 k
2.5 V 11 k 55 k 12 k 74 k
1.8 V 18 k 70 k 17 k 110 k
1.5 V 19 k 90 k 19 k 140 k
Notes:
1. R
(WEAK PULL-UP-MAX)
= (VCCI
MAX
– VOH
spec
) / I
(WEAK PULL-UP-MIN)
2. R
(WEAK PULL-DOWN-MAX)
= (VOL
spec
) / I
(WEAK PULL-DOWN-MIN)