ProASIC3 DC and Switching Characteristics
2-22 Revision 13
Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings
–2 Speed Grade, Commercial-Case Conditions: T
J
= 70°C, Worst Case VCC
= 1.425 V,
Worst-Case VCCI (per standard)
Advanced I/O Banks
I/O Standard
Drive Strength
Equiv. Software Default
Drive Strength Option
1
Slew Rate
Capacitive Load (pF)
External Resistor ()
t
DOUT
(ns)
t
DP
(ns)
t
DIN
(ns)
t
PY
(ns)
t
EOUT
(ns)
t
ZL
(ns)
t
ZH
(ns)
t
LZ
(ns)
t
HZ
(ns)
t
ZLS
(ns)
t
ZHS
(ns)
Units
3.3 V LVTTL /
3.3 V LVCMOS
12 mA 12 mA High 35 – 0.45 2.64 0.03 0.76 0.32 2.69 2.11 2.40 2.68 4.36 3.78 ns
3.3 V LVCMOS
Wide Range
2
100 µA 12 mA High 35 – 0.45 4.08 0.03 0.76 0.32 4.08 3.20 3.71 4.14 6.61 5.74 ns
2.5 V LVCMOS 12 mA 12 mA High 35 – 0.45 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 ns
1.8 V LVCMOS 12 mA 12 mA High 35 – 0.45 2.64 0.03 0.91 0.32 2.69 2.27 2.76 3.05 4.36 3.94 ns
1.5 V LVCMOS 12 mA 12 mA High 35 – 0.45 3.05 0.03 1.07 0.32 3.10 2.67 2.95 3.14 4.77 4.34 ns
3.3 V PCI Per
PCI
spec
– High 10 25
4
0.45 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns
3.3 V PCI-X Per
PCI-X
spec
– High 10 25
4
0.45 2.00 0.03 0.62 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns
LVDS 24 mA – High – – 0.45 1.37 0.03 1.20 – – – – – – – ns
LVPECL 24 mA – High – – 0.45 1.34 0.03 1.05 – – – – – – – ns
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-63 for
connectivity. This resistor is not required during normal operation.