ProASIC3 DC and Switching Characteristics
2-16 Revision 13
Figure 2-4 • Output Buffer Model and Delays (example)
t
DP
(R)
PAD
V
OL
t
DP
(F)
Vtrip
Vtrip
VOH
VCC
D
50%
50%
VCC
0 V
DOUT
50% 50%
0 V
t
DOUT
(R)
t
DOUT
(F)
From Array
PAD
t
DP
Std
Load
D
CLK
Q
I/O Interface
DOUT
D
t
DOUT
t
DP
= MAX(t
DP
(R), t
DP
(F))
t
DOUT
= MAX(t
DOUT
(R), t
DOUT
(F))