ProASIC3 DC and Switching Characteristics
2-14 Revision 13
User I/O Characteristics
Timing Model
Figure 2-2 • Timing Model
Operating Conditions: –2 Speed, Commercial Temperature Range (T
J
= 70°C), Worst Case
VCC = 1.425 V
DQ
Y
Y
DQ
DQ
DQ
Y
Combinational Cell
Combinational Cell
Combinational Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
Register Cell
Register Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
LVPECL (Applicable to
Advanced I/O Banks Only)L
LVPECL
(Applicable
to Advanced
I/O Banks only)
LVDS,
BLVDS,
M-LVDS
(Applicable for
Advanced I/O
Banks only)
LVTTL 3.3 V Output drive
strength = 12 mA High slew rate
Y
Combinational Cell
Y
Combinational Cell
Y
Combinational Cell
I/O Module
(Non-Registered)
LVTTL
Output drive strength = 8 mA
High slew rate
I/O Module
(Non-Registered)
LVCMOS 1.5 V
Output drive strength = 4 mA
High slew rate
LVTTL
Output drive strength = 12 mA
High slew rate
I/O Module
(Non-Registered)
Input LVTTL
Clock
Input LVTTL
Clock
Input LVTTL
Clock
t
PD
= 0.56 ns
t
PD
= 0.49 ns
t
DP
= 1.34 ns
t
PD
= 0.87 ns
t
DP
= 2.64 ns (Advanced I/O Banks)
t
PD
= 0.47 ns
t
DP
= 3.66 ns (Advanced I/O Banks)
t
PD
= 0.47 ns
t
DP
= 3.97 ns (Advanced I/O Banks)
t
PD
= 0.47 ns
t
PY
= 0.76 ns
(Advanced I/O Banks)
t
CLKQ
= 0.55 ns
t
OCLKQ
= 0.59 ns
t
SUD
= 0.43 ns
t
OSUD
= 0.31 ns
t
DP
= 2.64 ns
(Advanced I/O Banks)
t
PY
= 0.76 ns (Advanced I/O Banks)
t
PY
= 1.20 ns
t
CLKQ
= 0.55 ns
t
SUD
= 0.43 ns
t
PY
= 0.76 ns
(Advanced I/O Banks)
t
ICLKQ
= 0.24 ns
t
ISUD
= 0.26 ns
t
PY
= 1.05 ns