ProASIC3 DC and Switching Characteristics
2-12 Revision 13
Total Dynamic Power Consumption—P
DYN
P
DYN
= P
CLOCK
+ P
S-CELL
+ P
C-CELL
+ P
NET
+ P
INPUTS
+ P
OUTPUTS
+ P
MEMORY
+ P
PLL
Global Clock Contribution—P
CLOCK
P
CLOCK
= (P
AC1
+ N
SPINE
*P
AC2
+ N
ROW
*P
AC3
+ N
S-CELL
* P
AC4
) * F
CLK
N
SPINE
is the number of global spines used in the user design—guidelines are provided in the
"Spine Architecture" section of the Global Resources chapter in the ProASIC3 FPGA
Fabric User's Guide.
N
ROW
is the number of VersaTile rows used in the design—guidelines are provided in the "Spine
Architecture" section of the Global Resources chapter in the ProASIC3 FPGA Fabric
User's Guide.
F
CLK
is the global clock signal frequency.
N
S-CELL
is the number of VersaTiles used as sequential modules in the design.
P
AC1
, P
AC2
, P
AC3
, and P
AC4
are device-dependent.
Sequential Cells Contribution—P
S-CELL
P
S-CELL
= N
S-CELL
* (P
AC5
+
1
/ 2 * P
AC6
) * F
CLK
N
S-CELL
is the number of VersaTiles used as sequential modules in the design. When a multi-tile
sequential cell is used, it should be accounted for as 1.
1
is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-13.
F
CLK
is the global clock signal frequency.
Combinatorial Cells Contribution—P
C-CELL
P
C-CELL
= N
C-CELL
*
1
/ 2 * P
AC7
* F
CLK
N
C-CELL
is the number of VersaTiles used as combinatorial modules in the design.
1
is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-13.
F
CLK
is the global clock signal frequency.
Routing Net Contribution—P
NET
P
NET
= (N
S-CELL
+ N
C-CELL
) *
1
/ 2 * P
AC8
* F
CLK
N
S-CELL
is the number of VersaTiles used as sequential modules in the design.
N
C-CELL
is the number of VersaTiles used as combinatorial modules in the design.
1
is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-13.
F
CLK
is the global clock signal frequency.
I/O Input Buffer Contribution—P
INPUTS
P
INPUTS
= N
INPUTS
*
2
/ 2 * P
AC9
* F
CLK
N
INPUTS
is the number of I/O input buffers used in the design.
2
is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-13.
F
CLK
is the global clock signal frequency.
I/O Output Buffer Contribution—P
OUTPUTS
P
OUTPUTS
= N
OUTPUTS
*
2
/ 2 *
1
* P
AC10
* F
CLK
N
OUTPUTS
is the number of I/O output buffers used in the design.
2
is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-13.
1
is the I/O buffer enable rate—guidelines are provided in Table 2-17 on page 2-13.
F
CLK
is the global clock signal frequency.