• 当前位置:
  • 首页
  • >
  • PDF资料
  • >
  • A3P125-TQG100PP PDF文件及第13页内容在线浏览

A3P125-TQG100PP

A3P125-TQG100PP首页预览图
型号: A3P125-TQG100PP
PDF文件:
  • A3P125-TQG100PP PDF文件
  • A3P125-TQG100PP PDF在线浏览
功能描述: ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
PDF文件大小: 10669.38 Kbytes
PDF页数: 共220页
制造商: MICROSEMI[Microsemi Corporation]
制造商LOGO: MICROSEMI[Microsemi Corporation] LOGO
制造商网址: http://www.microsemi.com
捡单宝A3P125-TQG100PP
PDF页面索引
[1] 页[2] 页[3] 页[4] 页[5] 页[6] 页[7] 页[8] 页[9] 页[10] 页[11] 页[12] 页[13] 页[14] 页[15] 页[16] 页[17] 页[18] 页[19] 页[20] 页[21] 页[22] 页[23] 页[24] 页[25] 页[26] 页[27] 页[28] 页[29] 页[30] 页[31] 页[32] 页[33] 页[34] 页[35] 页[36] 页[37] 页[38] 页[39] 页[40] 页[41] 页[42] 页[43] 页[44] 页[45] 页[46] 页[47] 页[48] 页[49] 页[50] 页[51] 页[52] 页[53] 页[54] 页[55] 页[56] 页[57] 页[58] 页[59] 页[60] 页[61] 页[62] 页[63] 页[64] 页[65] 页[66] 页[67] 页[68] 页[69] 页[70] 页[71] 页[72] 页[73] 页[74] 页[75] 页[76] 页[77] 页[78] 页[79] 页[80] 页[81] 页[82] 页[83] 页[84] 页[85] 页[86] 页[87] 页[88] 页[89] 页[90] 页[91] 页[92] 页[93] 页[94] 页[95] 页[96] 页[97] 页[98] 页[99] 页[100] 页[101] 页[102] 页[103] 页[104] 页[105] 页[106] 页[107] 页[108] 页[109] 页[110] 页[111] 页[112] 页[113] 页[114] 页[115] 页[116] 页[117] 页[118] 页[119] 页[120] 页[121] 页[122] 页[123] 页[124] 页[125] 页[126] 页[127] 页[128] 页[129] 页[130] 页[131] 页[132] 页[133] 页[134] 页[135] 页[136] 页[137] 页[138] 页[139] 页[140] 页[141] 页[142] 页[143] 页[144] 页[145] 页[146] 页[147] 页[148] 页[149] 页[150] 页[151] 页[152] 页[153] 页[154] 页[155] 页[156] 页[157] 页[158] 页[159] 页[160] 页[161] 页[162] 页[163] 页[164] 页[165] 页[166] 页[167] 页[168] 页[169] 页[170] 页[171] 页[172] 页[173] 页[174] 页[175] 页[176] 页[177] 页[178] 页[179] 页[180] 页[181] 页[182] 页[183] 页[184] 页[185] 页[186] 页[187] 页[188] 页[189] 页[190] 页[191] 页[192] 页[193] 页[194] 页[195] 页[196] 页[197] 页[198] 页[199] 页[200] 页[201] 页[202] 页[203] 页[204] 页[205] 页[206] 页[207] 页[208] 页[209] 页[210] 页[211] 页[212] 页[213] 页[214] 页[215] 页[216] 页[217] 页[218] 页[219] 页[220] 页
120%
ProASIC3 Flash Family FPGAs
Revision 13 1-7
I/Os with Advanced I/O Standards
The ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V,
1.8 V, 2.5 V, and 3.3 V). ProASIC3 FPGAs support many different I/O standards—single-ended and
differential.
The I/Os are organized into banks, with two or four banks per device. The configuration of these banks
determines the I/O standards supported (Table 1-1).
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
Single-Data-Rate applications
Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications
ProASIC3 banks for the A3P250 device and above support LVPECL, LVDS, B-LVDS and M-LVDS.
B-LVDS and M-LVDS can support up to 20 loads.
Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card
in a powered-up system.
Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed
when the system is powered up, while the component itself is powered down, or when power supplies
are floating.
Wide Range I/O Support
ProASIC3 devices support JEDEC-defined wide range I/O operation. ProASIC3 supports the JESD8-B
specification, covering both 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V.
Wider I/O range means designers can eliminate power supplies or power conditioning components from
the board or move to less costly components with greater tolerances. Wide range eases I/O bank
management and provides enhanced protection from system voltage spikes, while providing the flexibility
to easily run custom voltage applications.
Specifying I/O States During Programming
You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for
PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.
Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have
limited display of Pin Numbers only.
1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during
programming.
2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator
window appears.
3. Click the Specify I/O States During Programming button to display the Specify I/O States During
Programming dialog box.
Table 1-1 • I/O Standards Supported
I/O Bank Type Device and Bank Location
I/O Standards Supported
LVTTL/
LVCMOS PCI/PCI-X
LVPECL, LVDS,
B-LVDS, M-LVDS
Advanced East and west Banks of A3P250 and
larger devices

Standard Plus North and south banks of A3P250 and
larger devices
All banks of A3P060 and A3P125

Not supported
Standard All banks of A3P015 and A3P030
Not
supported
Not supported
购买、咨询产品请填写询价信息:(3分钟左右您将得到回复)
询价型号*数量*批号封装品牌其它要求
删除
删除
删除
删除
删除
增加行数
  •  公司名:
  • *联系人:
  • *邮箱:
  • *电话:
  •  QQ:
  •  微信:

  • 关注官方微信

  • 联系我们
  • 电话:13714778017
  • 周一至周六:9:00-:18:00
  • 在线客服:

天天IC网由深圳市四方好讯科技有限公司独家运营

天天IC网 ( www.ttic.cc ) 版权所有©2014-2023 粤ICP备15059004号

因腾讯功能限制,可能无法唤起QQ临时会话,(点此复制QQ,添加好友),建议您使用TT在线询价。

继续唤起QQ 打开TT询价