ProASIC3 Flash Family FPGAs
Revision 13 2-107
Embedded FlashROM Characteristics
Timing Characteristics
Figure 2-43 • Timing Diagram
A
0
A
1
t
SU
t
HOLD
t
SU
t
HOLD
t
SU
t
HOLD
t
CKQ2
t
CKQ2
t
CKQ2
CLK
Address
Data
D
0
D
0
D
1
Table 2-124 • Embedded FlashROM Access Time
Parameter Description –2 –1 Std. Units
t
SU
Address Setup Time 0.53 0.61 0.71 ns
t
HOLD
Address Hold Time 0.00 0.00 0.00 ns
t
CK2Q
Clock to Out 21.42 24.40 28.68 ns
F
MAX
Maximum Clock Frequency 15 15 15 MHz