ProASIC3 Flash Family FPGAs
Revision 13 2-99
Figure 2-38 • FIFO Reset
Figure 2-39 • FIFO EMPTY Flag and AEMPTY Flag Assertion
MATCH (A
0
)
t
MPWRSTB
t
RSTFG
t
RSTCK
t
RSTAF
RCLK/
WCLK
RESET
EMPTY
AEMPTY
WA/RA
(Address Counter)
t
RSTFG
t
RSTAF
FULL
AFULL
RCLK
NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY)
t
CKAF
t
RCKEF
EMPTY
AEMPTY
t
CYC
WA/RA
(Address Counter)