ProASIC3 DC and Switching Characteristics
2-96 Revision 13
Table 2-117 • RAM512X18
Commercial-Case Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
Parameter Description –2 –1 Std. Units
t
AS
Address setup time 0.25 0.28 0.33 ns
t
AH
Address hold time 0.00 0.00 0.00 ns
t
ENS
REN, WEN setup time 0.13 0.15 0.17 ns
t
ENH
REN, WEN hold time 0.10 0.11 0.13 ns
t
DS
Input data (WD) setup time 0.18 0.21 0.25 ns
t
DH
Input data (WD) hold time 0.00 0.00 0.00 ns
t
CKQ1
Clock High to new data valid on RD (output retained) 2.16 2.46 2.89 ns
t
CKQ2
Clock High to new data valid on RD (pipelined) 0.90 1.02 1.20 ns
t
C2CRWH
1
Address collision clk-to-clk delay for reliable read access after write on same
address—Applicable to Opening Edge
0.50 0.43 0.38 ns
t
C2CWRH
1
Address collision clk-to-clk delay for reliable write access after read on same
address—Applicable to Opening Edge
0.59 0.50 0.44 ns
t
RSTBQ
RESET Low to data out Low on RD (flow-through) 0.92 1.05 1.23 ns
RESET Low to data out Low on RD (pipelined) 0.92 1.05 1.23 ns
t
REMRSTB
RESET removal 0.29 0.33 0.38 ns
t
RECRSTB
RESET recovery 1.50 1.71 2.01 ns
t
MPWRSTB
RESET minimum pulse width 0.21 0.24 0.29 ns
t
CYC
Clock cycle time 3.23 3.68 4.32 ns
F
MAX
Maximum frequency 310 272 231 MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.