ProASIC3 DC and Switching Characteristics
2-94 Revision 13
Timing Characteristics
Figure 2-34 • RAM Reset. Applicable to Both RAM4K9 and RAM512x18.
CLK
RESET
DOUT|RD
D
n
t
CYC
t
CKH
t
CKL
t
RSTBQ
D
m
Table 2-116 • RAM4K9
Commercial-Case Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
Parameter Description –2 –1 Std. Units
t
AS
Address setup time 0.25 0.28 0.33 ns
t
AH
Address hold time 0.00 0.00 0.00 ns
t
ENS
REN, WEN setup time 0.14 0.16 0.19 ns
t
ENH
REN, WEN hold time 0.10 0.11 0.13 ns
t
BKS
BLK setup time 0.23 0.27 0.31 ns
t
BKH
BLK hold time 0.02 0.02 0.02 ns
t
DS
Input data (DIN) setup time 0.18 0.21 0.25 ns
t
DH
Input data (DIN) hold time 0.00 0.00 0.00 ns
t
CKQ1
Clock High to new data valid on DOUT (output retained, WMODE = 0) 2.36 2.68 3.15 ns
Clock High to new data valid on DOUT (flow-through, WMODE = 1) 1.79 2.03 2.39 ns
t
CKQ2
Clock High to new data valid on DOUT (pipelined) 0.89 1.02 1.20 ns
t
C2CWWL
1
Address collision clk-to-clk delay for reliable write after write on same
address—Applicable to Closing Edge
0.33 0.28 0.25 ns
t
C2CWWH
1
Address collision clk-to-clk delay for reliable write after write on same
address—Applicable to Rising Edge
0.30 0.26 0.23 ns
t
C2CRWH
1
Address collision clk-to-clk delay for reliable read access after write on same
address—Applicable to Opening Edge
0.45 0.38 0.34 ns
t
C2CWRH
1
Address collision clk-to-clk delay for reliable write access after read on same
address— Applicable to Opening Edge
0.49 0.42 0.37 ns
t
RSTBQ
RESET Low to data out Low on DOUT (flow-through) 0.92 1.05 1.23 ns
RESET Low to Data Out Low on DOUT (pipelined) 0.92 1.05 1.23 ns
t
REMRSTB
RESET removal 0.29 0.33 0.38 ns
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.