SmartFusion DC and Switching Characteristics
2-70 Revision 10
Table 2-88 • RAM512X18
Worst Commercial-Case Conditions: T
J
= 85°C, Worst-Case VCC = 1.425 V
Parameter Description –1 Std. Units
t
AS
Address setup time 0.25 0.30 ns
t
AH
Address hold time 0.00 0.00 ns
t
ENS
REN, WEN setup time 0.09 0.11 ns
t
ENH
REN, WEN hold time 0.06 0.07 ns
t
DS
Input data (WD) setup time 0.19 0.22 ns
t
DH
Input data (WD) hold time 0.00 0.00 ns
t
CKQ1
Clock High to new data valid on RD (output retained, WMODE = 0) 2.19 2.63 ns
t
CKQ2
Clock High to new data valid on RD (pipelined) 0.91 1.09 ns
t
C2CRWH
1
Address collision clk-to-clk delay for reliable read access after write on same
address—applicable to opening edge
0.38 0.43 ns
t
C2CWRH
1
Address collision clk-to-clk delay for reliable write access after read on same
address—applicable to opening edge
0.44 0.50 ns
t
RSTBQ
RESET Low to data out Low on RD (flow-through) 0.94 1.12 ns
RESET Low to data out Low on RD (pipelined) 0.94 1.12 ns
t
REMRSTB
RESET removal 0.29 0.35 ns
t
RECRSTB
RESET recovery 1.52 1.83 ns
t
MPWRSTB
RESET minimum pulse width 0.22 0.22 ns
t
CYC
Clock cycle time 3.28 3.28 ns
F
MAX
Maximum clock frequency 305 305 MHz
Notes:
1. For more information, refer to the Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-Based cSoCs and
FPGAs application note.
2. For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for
derating values.