SmartFusion DC and Switching Characteristics
2-58 Revision 10
Timing Characteristics
Figure 2-26 • Timing Model and Waveforms
PRE
CLR
Out
CLK
Data
EN
t
SUE
50%
50%
t
SUD
t
HD
50%
50%
t
CLKQ
0
t
HE
t
RECPRE
t
REMPRE
t
RECCLR
t
REMCLRt
WCLR
t
WPRE
t
PRE2Q
t
CLR2Q
t
CKMPWH
t
CKMPWL
50% 50%
50%
50%
50%
50% 50%
50%
50%
50% 50%
50%
50%
50%
50%
Table 2-79 • Register Delays
Worst Commercial-Case Conditions: T
J
= 85°C, Worst-Case VCC = 1.425 V
Parameter Description –1 Std. Units
t
CLKQ
Clock-to-Q of the Core Register 0.56 0.67 ns
t
SUD
Data Setup Time for the Core Register 0.44 0.52 ns
t
HD
Data Hold Time for the Core Register 0.00 0.00 ns
t
SUE
Enable Setup Time for the Core Register 0.46 0.55 ns
t
HE
Enable Hold Time for the Core Register 0.00 0.00 ns
t
CLR2Q
Asynchronous Clear-to-Q of the Core Register 0.41 0.49 ns
t
PRE2Q
Asynchronous Preset-to-Q of the Core Register 0.41 0.49 ns
t
REMCLR
Asynchronous Clear Removal Time for the Core Register 0.00 0.00 ns
t
RECCLR
Asynchronous Clear Recovery Time for the Core Register 0.23 0.27 ns
t
REMPRE
Asynchronous Preset Removal Time for the Core Register 0.00 0.00 ns
t
RECPRE
Asynchronous Preset Recovery Time for the Core Register 0.23 0.27 ns
t
WCLR
Asynchronous Clear Minimum Pulse Width for the Core Register 0.22 0.22 ns
t
WPRE
Asynchronous Preset Minimum Pulse Width for the Core Register 0.22 0.22 ns
t
CKMPWH
Clock Minimum Pulse Width High for the Core Register 0.32 0.32 ns
t
CKMPWL
Clock Minimum Pulse Width Low for the Core Register 0.36 0.36 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.