DQ
Y
Y
DQ
DQ
DQ
Y
Combinational Cell
Combinational Cell
Combinational Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
Register Cell
Register Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
LVPECL (applicable to
FPGA /O bank, EMC pin)
LVPECL
(Applicable
to FPGA
I/O Bank,
EMC pin)
LVDS,
BLVDS,
M-LVDS
(Applicable for
FPGA I/O Bank,
EMC pin)
LVTTL 3.3 V Output drive
strength = 12 mA High slew rate
Y
Combinational Cell
Y
Combinational Cell
Y
Combinational Cell
I/O Module
(Non-Registered)
LVTTL
Output drive strength = 8 mA
High slew rate
I/O Module
(Non-Registered)
LVCMOS 1.5 V
Output drive strength = 4 mA
High slew rate
LVTTL
Output drive strength = 12 mA
High slew rate
I/O Module
(Non-Registered)
Input LVTTL
Clock
Input LVTTL
Clock
Input LVTTL
Clock
t
PD
= 0.57 ns
t
PD
= 0.49 ns
t
DP
= 1.53 ns
t
PD
= 0.89 ns
t
DP
= 2.81 ns (FPGA I/O Bank, EMC pin)
t
PD
= 0.51 ns
t
DP
= 3.87 ns (FPGA I/O Bank, EMC pin)
t
PD
= 0.48 ns
t
DP
= 4.13 ns (FPGA I/O Bank, EMC pin)
t
PD
= 0.48 ns
t
PY
= 0.81 ns
(FPGA I/O Bank, EMC pin)
t
CLKQ
= 0.56 ns
t
OCLKQ
= 0.60 ns
t
SUD
= 0.44 ns
t
OSUD
= 0.32 ns
t
DP
= 2.81 ns
(FPGA I/O Bank, EMC pin)
t
PY
= 0.81 ns (FPGA I/O Bank, EMC pin)
t
PY
= 1.55 ns
t
CLKQ
= 0.56 ns
t
SUD
= 0.44 ns
t
PY
= 0.81 ns
(FPGA I/O Bank, EMC pin)
t
ICLKQ
= 0.24 ns
t
ISUD
= 0.27 ns
t
PY
= 1.46 ns