SmartFusion Customizable System-on-Chip (cSoC)
Revision 10 2-11
Table 2-11 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Applicable to MSS I/O Banks
VCCMSSIOBx (V)
Static Power
PDC7 (mW)
Dynamic Power
PAC9 (µW/MHz)
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 17.21
3.3 V LVCMOS / 3.3 V LVCMOS – Schmitt trigger 3.3 – 20.00
2.5 V LVCMOS 2.5 – 5.55
2.5 V LVCMOS – Schmitt trigger 2.5 – 7.03
1.8 V LVCMOS 1.8 – 2.61
1.8 V LVCMOS – Schmitt trigger 1.8 – 2.72
1.5 V LVCMOS (JESD8-11) 1.5 – 1.98
1.5 V LVCMOS (JESD8-11) – Schmitt trigger 1.5 – 1.93
Table 2-12 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings
*
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
C
LOAD
(pF)
VCCFPGAIOBx
(V)
Static Power
PDC8 (mW)
Dynamic Power
PAC10 (µW/MHz)
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 – 475.66
2.5 V LVCMOS 35 2.5 – 270.50
1.8 V LVCMOS 35 1.8 – 152.17
1.5 V LVCMOS (JESD8-11) 35 1.5 – 104.44
3.3 V PCI 10 3.3 – 202.69
3.3 V PCI-X 10 3.3 – 202.69
Differential
LVDS – 2.5 7.74 88.26
LVPECL – 3.3 19.54 164.99
Note: *Dynamic power consumption is given for standard load and software default drive strength and output slew.
Table 2-13 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings
Applicable to MSS I/O Banks
C
LOAD
(pF) VCCMSSIOBx (V)
Static Power
PDC8 (mW)
2
Dynamic Power
PAC10 (µW/MHz)
3
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS 10 3.3 – 155.65
2.5 V LVCMOS 10 2.5 – 88.23
1.8 V LVCMOS 10 1.8 – 45.03
1.5 V LVCMOS (JESD8-11) 10 1.5 – 31.01